Exact compiler-owned identities used by architecture intrinsic helpers. Source helpers.rs::get_twice_wide_int_ty and project_to_simd.

def Miri.Input.CompilerArchitectureFacts.integerLayout (runtime : RuntimeMetadata) (bits : Nat) (signed : Bool) : Except String Interpreter.LocalLayout

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def Miri.Input.CompilerArchitectureFacts.integerLayoutContext (context : CompilerFacts.Context) (bits : Nat) (signed : Bool) : Except String Interpreter.LocalLayout

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def Miri.Input.CompilerArchitectureFacts.twiceWideLayout (runtime : RuntimeMetadata) (id : MIR.TyId) : Except String Interpreter.LocalLayout

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def Miri.Input.CompilerArchitectureFacts.twiceWideLayoutContext (context : CompilerFacts.Context) (id : MIR.TyId) : Except String Interpreter.LocalLayout

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def Miri.Input.CompilerArchitectureFacts.isSimd (context : CompilerFacts.Context) (id : MIR.TyId) : Except String Bool

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• Miri.Input.CompilerArchitectureFacts.isSimd context id = Miri.Input.CompilerFacts.boolean context id "is_simd"

def Miri.Input.CompilerArchitectureFacts.simdSizeAndType (context : CompilerFacts.Context) (id : MIR.TyId) : Except String (UInt64 × MIR.TyId)

Query payload contains actual compiler lane count and element identity; backend vector size does not establish either source property.

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def Miri.Input.CompilerArchitectureFacts.simdHooks {P S C V : Type} (context : CompilerFacts.Context) (base : Interpreter.IntrinsicSimdHooks P S C V) : Interpreter.IntrinsicSimdHooks P S C V

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